Air Warfare Destroyer low-band ES
Firmware design of the AWD low-band ES system for Jenkins Engineering Defence Services (JEDS):
- Xilinx Virtex 6 FPGA design.
- Multi-channel ES (Electronics Surveillance) system DSP design.
- Design of Pulse Descriptor Word generation algorithms.
- Design of Modulation on pulse detection algorithms.
Generic Missile HIL Testing DRFM
Design and implementation of the Digital RF Memory (DRFM) based Radar Target Generator for Missile Simulation Centre Upgrade Program at Defence Science and Technology Group, Australia:
- Tekmicro Virtex 5 Triton board was used to implement a radar scene generator.
- Signal processing and system design.
- FPGA design: implementation of scene generator algorithms.
- Software interface design.
- System test and integration.
Air Warfare Destroyer narrow-band ES
AWD narrow-band ES receiver design program:
- Tekmicro ProteusV6 module programming support.
- Communications interface design.
- ES algorithm design.
- Modulation on pulse detection and classification.
- Frequency modulation on pulse.
- Phase modulation on pulse.
DM3 Software Define Radio
Development of Satellite Communications Waveforms for the Defence Multi-Mode Modem (DM3) Software Defined Radio project for Auspace Limited:
- Digital signal processing algorithm design.
- Real-time software design.
- Algorithm optimisation.
- Hardware integration.
- Test and verification.
Missile Seeker HIL Test Radar RTG
Implemented a Radar Target Generator for Weapon System Division at Defence Science and Technology Group for use as a hardware-in-the-loop (HIL) testing of missile seekers:
- Digital RF Memory (DRFM) algorithm design.
- Tenix (now BAE) wide-band Digital RF Processor System was used to implement the digital processing.
- Electronics Counter Measures (ECM) techniques development.
- RF transmitter, receiver design.
802.11 on an ASIC SDR
Design and implementation of a WiFi 802.11 based physical layer on a Software Design Radio (SDR) for CohdaWireless:
- Complex signal processing algorithm design and implementation on a vectorised DSP.
- Optimisation of signal processing algorithms into embedded processing device.
- Integration of the physical layer with higher level protocol stack to work as a WiFi system.
Synthetic Aperture Radar Frontend
Implementation of a Radar signal capture device for Information Surveillance and Reconnaissance Divisions at Defence Science and Technology Group:
- Interfacing of very high speed (3 GSPS) analogue-to-digital converters to Xilinx Virtex 5 FPGA.
- Design and implementation of multiple samples per clock Finite Impulse Response (FIR) filters on FPGAs with software reconfigurable filter coefficients.
- Design and implementation of high speed data acquisition system with filtering functionality.